1. Field of the Invention
The present invention relates to a semiconductor memory, or more particularly, to a semiconductor memory having a redundancy circuit.
2. Description of the Related Art
A redundancy circuit is used to replace a defective cell included in a memory, or especially, a dynamic RAM with a redundancy cell.
For preventing establishment of a multiword state, in which both a normal word line and a redundancy word line are activated, during such replacement of a defective cell, activation of a normal word line is retarded until it is judged whichever of a redundancy word line and the normal word line should be activated. In recent years, it has been requested to shorten a time interval from the instant an address is supplied to the instant data stored in memory cell is read out based on the address.
FIG. 8 is a circuit diagram showing an example of a related art circuit. FIG. 9 is a timing chart showing the waveforms of signals produced in the circuitry.
First, external address signals A0 to Aj are stored in row address buffers 110. The row address buffers 110 acquire the external address signals A0 to Aj at the leading edge of an external address latching signal ECLK. Row address signals XA0 to XAj output from the row address buffers 110 are input to an address judgment circuit 130 and address pre-decoders 120. The address judgment circuit 130 compares the row address signals XA0 to XAj with a pre-set address in response to a redundancy latching signal. If the row address signals XA0 to XAj agree with the pre-set address, a redundancy judgment signal AC remains active (solid line in AC in FIG. 9). If the row address signals XA0 to XAj disagree with the pre-set address, the redundancy judgment signal AC is inactive (dashed line in AC in FIG. 9). A redundancy control circuit 140 reads the redundancy judgment signal AC at the leading edge of a row address latching signal RCLK' after address judgment is completed, and then judges whether a redundancy word line should be activated. At this time, an address pre-decoder 120 acquires signals resulting from pre-decoding of the row address signals XA0 to XAj and outputs address pre-decoded signals PXA0 to PXAk to a normal word decoder 160. Either of a normal word line and a redundancy word line is activated based on a redundancy word enabling signal RDC and a normal word enabling signal XDES that are output signals of the redundancy control circuit 140.
According to the related art shown in FIG. 8 and FIG. 9, for preventing establishment of a multiword state, both the normal word decoder 160 and redundancy word decoder 150 are held unselected until a time instant when it is judged whichever of a normal word line and a redundancy word line should be activated. After the judgment is made, the row address latching signal RCLK', which is a delayed row address latching signal, is driven high, and either of the normal word decoder 160 and redundancy word decoder 150 is selected. For example, The redundancy control circuit produces the signal XDES of a low logic level at first. Then, the redundancy control circuit changes the level of the signal XDES from the low logic level to a high logic level when the redundancy control circuit receives the rising edge of the signal RCLK' and the signal AC indicating that an addressed memory cell is not a defective cell. On the other hand, the normal word line decoder does not select any normal word lines at all when the normal word line decoder receives the signal XDES of the low logic level. The normal word line decoder selects one of the normal word lines in response to the address PXA0.about.PXAk after the level of the signal XDES changes from the low logic level to the high logic level. The time required for activating a normal word line is therefore dependent on the normal word enabling signal XDES indicating the results of the judgment. However, the number of normal word lines is larger than the number of redundancy word lines. The number of stages of logic circuits included in the normal word decoder 160 is much larger than that included in the redundancy word decoder 150. As shown in FIG. 9, it takes much time to activate a normal word line. Quick access to a memory cell has therefore been disabled in the past.